Olejar Books

All papers were peer reviewed. This proceedings presents current research on issues related to stress-induced phenomena in on-chip metal interconnects and solder joints. Stresses arising in on-chip metal interconnects and surrounding dielectric materials due to thermal mismatch, electromigration, microstructure changes or process integration can lead to degradation and failure of microelectronic products. The implementation of low dielectric constant materials into the inlaid copper backend-of-line process has brought new challenges for process integration and reliability. Stress in solder joints can cause metallurgic effects like whisker growth, and subsequently failure. Understanding stress-related phenomena in new materials and structures is critical for development and integration of future metallic structures in microelectronic products.